Facts checked on 20 October 2026

Short answer

On 20 October 2026 Qorvo’s product pages showed the two-antenna DW3120 (WLCSP) and DW3220 (QFN) in “Last Time Buy” under PCN 26-0105, with a last time buy on 28 February 2027 and no replacement named. The single-antenna DW3110 and DW3210 remain in production.

The QM33110W and QM33120W are a newer silicon revision on the same 52-ball WLCSP ball map and the same SDK, but GPIO functions, the SPI clock limit, SPI mode set-up and register addresses differ. No QM33 part comes in QFN, so a DW3220 board needs a new layout.

Lifecycle status on 20 October 2026

PartPackage, RF portsStatus on qorvo.comNotes
DW3120WLCSP 3.1 x 3.4 mm, 2 ports (PDoA)Last Time Buy“End of Life announced August 3, 2026”, PCN 26-0105; last time buy 28 Feb 2027
DW3220QFN 5.0 x 5.0 mm, 2 ports (PDoA)Last Time BuySame PCN and dates
DW3110WLCSP 3.1 x 3.4 mm, 1 portProductionNo notice
DW3210QFN 5.0 x 5.0 mm, 1 portProductionNo notice
QM33110WWLCSP 3.1 x 3.4 mm, 1 portProductionChannel 9 “Japan support”
QM33120WWLCSP 3.1 x 3.4 mm, 2 ports (PDoA)ProductionChannel 9 “Japan support”
DWM3000, DWM3001C modulesModules built on the DW3110ProductionNot covered by the notice
DWM3001CDK, QM33120WDK1 kitsDevelopment kitsProductionBoth list “DW3xxx & QM3xxx SDK v1.1.1”

Package sizes are as listed on the product pages. The DW3000 and QM33120W data sheets give the 52-ball WLCSP as 3.1 mm x 3.5 mm, so take footprint dimensions from the data sheet drawings.

Neither end-of-life page names a replacement; both say “Contact your local sales representative for assistance.” The whole DW3000 family is not end of life: two of its four parts are, and the modules use a part that is still in production.

What PCN 26-0105 means for a shipping product

On the day we checked, about 19 weeks remained until the last time buy on 28 February 2027. The product pages link the PCN to Qorvo’s PCN Alert portal rather than publishing it, so they are the public record we used. They do not show a last ship date. In an earlier notice, PCN 25-0154 for the MDEK1001 kit, Qorvo made end-of-life orders “non-cancellable, non-returnable (NCNR)” and gave a separate last ship date. Read PCN 26-0105 through your distributor or the portal for its own terms before you size a buy.

A product team usually has three decisions to make, product by product:

  • How much stock to buy, if any, and who holds it.
  • Which target part a redesign uses, and whether the board survives.
  • When the redesigned product must be certified, so that it ships before the stock runs out.

Part-by-part mapping

FromPackageUsual targetBoard impactComment
DW3120WLCSP-52QM33120WSame ball map; GPIO roles changeThe shortest path
DW3220QFN-40QM33120WNew footprint and layoutNo QFN QM33 part exists
DW3110WLCSP-52Stay, or QM33110WSame ball mapMove for Japan or for new designs
DW3210QFN-40Stay, or QM33110WNew footprint and layoutStill in production
DWM3000, DWM3001CModuleNo change forcedNoneBuilt on the DW3110

DW3120 to QM33120W: same ball map, newer silicon

A Qorvo staff reply on the Qorvo Tech Forum (July 2025) describes the QM33 as “a newer silicon revision than the DW3000 series to support Japan pulse shape” and states that the DW3000 is available “in both a QFN and a pin2pin compatible CSP”. We compared the ball tables of the DW3000 and QM33120W data sheets: every signal, from IRQ on B1 and the SPI pins to RF1 on H11 and RF2 on H5, sits on the same ball. Qorvo’s own wording is careful, though. The QM33120W data sheet calls the part “compatible with the DW3000 product line with some differences primarily related to GPIO functionality”, and an earlier staff reply notes that “registers may be added/updated”. Pin compatible means the footprint can stay. It does not mean the schematic, firmware or certification stay.

DW3220 to QM33120W: a new layout

Qorvo lists no QM33 part in QFN. Both QM33 product pages show only the WLCSP, and the same staff reply says “QM33 is only available in CSP package”. A DW3220 board therefore needs a new footprint, fan-out and RF routing. The stack-up changes as well: the DW3000 data sheet recommends a four-layer board with through vias for the QFN variant, while the layout in the QM33120W data sheet uses six layers with micro-vias on pad. Price that PCB technology early.

If moving to a WLCSP is not possible, one alternative is a module. Murata’s Type 2AB combines the QM33120W with an nRF52840 host in 10.5 x 8.3 x 1.44 (max) mm. That changes your host processor too.

DW3110 and DW3210: no forced move

Both single-port parts showed “Production” with no notice. Teams on them have time to plan. There are two reasons to move anyway: Japan, where the DW3xxx parts cannot meet the pulse-shape rules and the QM33 parts can (see below), and new product generations.

Hardware differences that need schematic or layout changes

GPIO4, GPIO5 and GPIO6 change roles

This is the change most likely to break an existing board. External front-end modules (PA, LNA, switch) are usually driven from these pins, and their functions moved.

Pin (WLCSP ball)DW3000 data sheetQM33120W data sheet
GPIO4 (F1)EXTPA, external power amplifierCOEXIN, EXTTXE, PDoA_SW0 (on during a TX frame)
GPIO5 (D1)EXTTXE; SPIPOL strap at power-upCOEX_OUT, EXTRXE, PDoA_SW1 (high before RX)
GPIO6 (C4)EXTRXE; SPIPHA strap at power-upEXTSWRX, PDoA_SW2 (RF port 1 switching)

Qorvo’s driver confirms it. In the DW3000 driver, ull_setlnapamode() maps DWT_PA_ENABLE to GPIO4 (EXTPA) and GPIO5 (EXTTXE), and DWT_LNA_ENABLE to GPIO6 (EXTRXE). In the QM33 driver (named dw3720), DWT_PA_ENABLE drives GPIO4 and DWT_LNA_ENABLE drives GPIO5, and GPIO6 is not touched. In practice, a front end whose TX enable is wired to GPIO5 and RX enable to GPIO6 must be rewired to GPIO4 and GPIO5. Asked about a front end that behaved differently on the two families, Qorvo staff pointed to these pins in April 2026 and to “the ull_setlnapamode function in dw3720_device.c and dw3000_device.c”.

SPI clock limit and SPI mode

  • Clock. The DW3000 data sheet (version 1.3) allows SPI clock frequencies “up to 36MHz”; the QM33110W and QM33120W data sheets allow “up to 32 MHz”. If your host runs the fast SPI phase above 32 MHz, lower it. Both data sheets specify 7 MHz SPI in INIT_RC, so the slow-then-fast start-up stays.
  • Mode. On the DW3000, GPIO5 (SPIPOL) and GPIO6 (SPIPHA) are sampled at power-up; they are pulled low for mode 0, and other modes need pull-ups of no more than 10 kΩ to VIO_D. On the QM33, “Mode 0 is the default mode”, the mode “can be changed by programming in the OTP memory or writing to the appropriate register”, and the boot mode “cannot be configured by GPIO states at power on”. A board that strapped GPIO5 or GPIO6 high for mode 1, 2 or 3 will come up in mode 0 on a QM33. Either move the host to mode 0 and remove the straps, which now sit on front-end pins, or program the mode into OTP once per unit.

RF filtering for regional compliance

Japan is the clearest case. A Qorvo staff reply in 2024 states that “DW3xxx does not support a pulse shape which can comply with ARIB STD-T91”, the Japanese standard. Another reply confirms that the DW3110 does not support it and that “you would need the QM33110/20”. Qorvo’s API guide adds dwt_set_alternative_pulse_shape(), “only supported in DW3720 (E0) silicon” and designed for ARIB on channel 9. For ARIB, Qorvo staff “strongly recommend using a bandpass filter to suppress out of band emissions”, say the QM33120WDK1 uses the same kind of filter (LFB217G35CFHE826) and note that peak power is measured with a 50 MHz resolution bandwidth against a 0 dBm/50 MHz limit.

The QM33 data sheets also list “Japan and Korea regulatory compliance”. We found no public Qorvo statement on whether a transmit filter is required for Korea, so confirm that with Qorvo and your test laboratory. The DW3000 data sheet adds a general note: a band-pass filter on RF1/RF2 “may be required for certification in some regions that mandate conducted testing”.

What stays the same

Supply ranges (VDD1 1.62–3.6 V, VDD2a/b 2.4–3.6 V, VDD3 1.5–3.6 V), the 38.4 MHz crystal, the 2 pF capacitor on each used RF port and the 50 Ω termination of an unused RF2 are common to both data sheets. Typical deep-sleep current drops from 260 nA (DW3000) to 210 nA (QM33).

Firmware differences in the DW3_QM33 SDK and driver

One SDK, two device drivers

Qorvo’s DW3_QM33 SDK serves both families. The v1.0.2 release supported “QM33120W, QM33110W, DW3120, DW3110, DW3220, DW3210”, and today the four DW3xxx product pages and the QM33120WDK1 kit page list “DW3xxx & QM3xxx SDK v1.1.1”. It is a download from qorvo.com: Qorvo’s public GitLab group had no DW3_QM33 project on 20 October 2026. Qorvo staff wrote in 2025 that because recent drivers “support both QM33 and DW3000, it is very simple to move from one device to the other in the software”, and in 2026 that DW3110, DW3120, DW3210 and DW3220 “should use dw3000 device driver” while QM33110W and QM33120W “should use dw3720 device driver”.

dwt_probe() reads the device ID and binds whichever driver in its list matches. The driver headers define these IDs:

PartDEV_IDDriver
DW3110, DW32100xDECA0302dw3000
DW3120, DW32200xDECA0312dw3000
QM33110W0xDECA0304dw3720
QM33120W0xDECA0314dw3720

Each driver descriptor masks the PDoA digit (devmatch 0xFFFFFF0F), so one descriptor covers both variants of a family. A product that links only dw3000_driver will fail to probe a QM33.

Register-level code

Code that bypasses the API needs review. In the driver register headers, CHAN_CTRL moves from 0x10014 to 0x10008 and TX_POWER from 0x1000C to 0x10004. A staff reply confirms that some register addresses changed, citing the channel control register at 0x10008, and Qorvo staff point QM33 users to the QM33100 User Manual for register details.

Configuration and calibration values

  • OTP layout carries over. Both drivers read LDO tune (0x04, 0x05), crystal trim (0x1E), bias tune (0x0A), DGC tuning (from 0x20) and the PLL lock code (0x35) from the same OTP addresses, so a production flow that writes crystal trim to OTP keeps its address.
  • Receiver tuning differs. The API guide lists different DGC look-up values for DW3000 and DW3720; the driver applies them, so do not copy tables between families.
  • Calibration behaviour differs. The API guide notes that ADC calibration can only be done on DW3720-based chips, and the DWT_PGFCAL bit of dwt_configuresleep() “has the opposite function” on DW3720. The driver clears it, but code that sets wake-up bits by hand should be checked.
  • Unit calibration starts again. Antenna delay, PDoA offset and transmit power are board and chip dependent. The QM33120W data sheet states PDoA accuracy per channel, frame length and PDoA mode (±12.5° on channel 9 with 128/256 symbols, “TBC” on channel 5), so re-run your angle calibration rather than reusing DW3120 tables.

An illustrative sketch of a firmware image that supports both families during the transition:

/* Illustrative: one image for DW3xxx and QM33 boards (DW3_QM33 SDK driver API). */
extern const struct dwt_driver_s dw3000_driver;  /* DW3110, DW3120, DW3210, DW3220 */
extern const struct dwt_driver_s dw3720_driver;  /* QM33110W, QM33120W */
static struct dwt_driver_s *drivers[] = {
    (struct dwt_driver_s *)&dw3000_driver,
    (struct dwt_driver_s *)&dw3720_driver };

/* probe_interf.driver_list = drivers; probe_interf.dw_driver_num = 2; */
if (dwt_probe(&probe_interf) != DWT_SUCCESS) {
    return -1;                       /* DEV_ID unreadable or not in the list */
}
uint32_t id = dwt_readdevid();
bool qm33 = (id == (uint32_t)DWT_QM33110_DEV_ID) ||
            (id == (uint32_t)DWT_QM33120_PDOA_DEV_ID);

dwt_setfinegraintxseq(0);            /* required before enabling an external PA */
dwt_setlnapamode(DWT_LNA_ENABLE | DWT_PA_ENABLE);
/* DW3xxx: PA on GPIO4 (EXTPA) and GPIO5 (EXTTXE), LNA on GPIO6 (EXTRXE).
 * QM33:   PA on GPIO4, LNA on GPIO5. The board wiring must match the chip. */
if (qm33 && build_for_japan) {
    dwt_set_alternative_pulse_shape(1);  /* ARIB STD-T91 shape, channel 9 */
}

What must be re-tested and re-certified

AreaWhy the chip change mattersWhat to plan
Radio regulationNew silicon, new pulse shape options and possibly a new front end; the QM33 data sheets say the part “has not been certified for use in any particular geographic region”New tests per market: ETSI EN 302 065-1 in the EU, 47 CFR 15.519 for handheld devices in the US (−41.3 dBm/MHz average EIRP), ARIB STD-T91 in Japan
FiRa“Any changes made to a previously-certified device will require re-certification”; results may be inherited “on a case-by-case basis”Re-certify listed products; never claim the logo for an uncertified build
Apple Nearby InteractionBoth families are listed as “Interoperable with Apple U1 & U2 chip”, but the firmware build changesRe-run phone tests; Apple tells accessory makers to “Contact your UWB chipset vendor to confirm feature support”
Android and other FiRa peersSession parameters and vendor-specific settings move with the firmwareRe-run interoperability against each phone and peer you support
Production testCalibration values and limits changeRe-baseline using Qorvo’s APS312 note, which is listed on both families’ pages
Mixed fleetsDW3xxx and QM33 devices will range together for a whileTest every pair of hardware and firmware you will field

How a migration runs: four stages with checks

1. Assessment (2–4 weeks)

Inventory every product with a DW3xxx part: package, RF ports used, front end, SPI mode and clock, SDK and driver version, register-level code, calibration flow, certificates and markets. Count stock, forecast and the date the redesigned product must ship.

  • Deliverables: per-product decision (buy, redesign to QM33, other route), sized plan, list of hardware and firmware changes.
  • Exit check: every shipped radio configuration and front-end wiring is known, and the last-time-buy quantity is backed by a dated certification plan.

2. Phased port

  1. Schematic and layout: front-end enables moved to GPIO4 and GPIO5, SPI straps removed or OTP programming planned, RF filter for Japan if needed; a new footprint for QFN boards.
  2. Bring-up: both drivers in the probe list, ID logged, SPI at 32 MHz or less, PLL lock, crystal trim.
  3. Driver and configuration: remove or port register-level code; check every dwt_configure() return code.
  4. Calibration and production test: antenna delay, PDoA, transmit power, OTP writes.
  5. Builds per market: alternative pulse shape for Japan only where certified.
  • Exit check: every board passes bring-up, and DW3xxx and QM33 units range with each other in your session profile.

3. Validation on hardware

TestSet-upPass criterion
RangingOld and new units at surveyed distances, LOS and NLOSMean error and spread no worse than the DW3xxx baseline
AngleTurntable or fixed angles across the field of view, per channelError within your product requirement, per PDoA mode
Front endScope GPIO4/5 against TX and RXEnables switch before the first TX pulse and before RX
SPILong transfers at the chosen clock and temperature extremesNo read-back errors
InteroperabilityPhones and peers you supportAll sessions start and report
PowerFull ranging cycle and sleepBattery life meets the requirement
  • Exit check: every test passes or has an agreed waiver, with raw data kept.

4. Certification and transition

Run the radio, FiRa and phone work from the table above, freeze the certified build and plan the switch-over so that last-time-buy stock covers the gap.

Decision criteria: stock, redesign to QM33 or QM35825

RouteFits whenWhat it costs you
Last-time-buy stockThe product ends within the stock’s life, or a redesign is planned anywayCash tied up in stock, storage and handling, no Japan market
DW3120 board to QM33120WYou need PDoA and own your firmwareFront-end rewiring, SPI and driver changes, recalibration, re-certification
DW3220 board to QM33120WAs above, on a QFN boardPlus a new layout and probably a finer PCB technology
Drop to DW3110 or DW3210The second port is not used for PDoARF2 termination change; still no Japan
QM35825 SoCYou need 3D angle of arrival, radar or a part listed with FiRa 3.0 certificationBGA-74, four RF ports, Qorvo’s pre-compiled firmware and a host-based application

On the last row, a Qorvo staff reply from 2025 states that “generating your own software running on the QM35825 is not possible and you must use the pre-compiled software from Qorvo”, so code written for the DW3xxx driver does not carry over.

needCode’s view for new designs

For new designs we recommend the QM33 family rather than DW3xxx parts. Two DW3xxx parts already carry an end-of-life notice, the QM33 parts run on the same SDK and driver package, and unlike the DW3xxx parts the QM33 offers the ARIB STD-T91 pulse shape for Japan. This is our engineering view, not a Qorvo statement.

Typical failures and how to confirm them

SymptomLikely causeHow to confirmFix
dwt_probe() fails on new boardsdw3720_driver missing from the listLog dwt_readdevid(): 0xDECA0304 or 0xDECA0314Add the driver
SPI errors at full speedHost clock above 32 MHzError rate falls when the clock dropsLimit SPI to 32 MHz
No SPI response after resetBoard relies on GPIO5/6 straps for a non-zero modeWorks in mode 0Use mode 0 or program OTP
No transmit or no receive with a front endEnables wired to DW3xxx GPIO rolesScope GPIO4/5/6 during TX and RXRewire, or drive the front end yourself
Register writes ignoredHard-coded DW3000 addressesCompare with the dw3720 register headerUse API calls or new addresses
Angle offset after migrationDW3120 PDoA calibration reusedMeasure at known anglesRecalibrate per channel and mode
Japan emission test failsStandard pulse shape or no filterCheck the build flag and RF pathEnable the alternative shape; add the filter

One developer on Qorvo’s forum reported a front end that worked on a QM33110W board and failed on a DW3000-family board with the same firmware. The same GPIO difference works in both directions.

What to prepare

  • BOM, schematic, layout, stack-up and front-end data sheets.
  • Firmware repositories, SDK and driver versions, and any code that writes registers directly.
  • Host SPI configuration (mode, clock) and the strap resistors on GPIO5 and GPIO6.
  • Calibration procedure, OTP usage and production test scripts.
  • Certificates, test reports and the list of markets, including Japan and Korea.
  • Stock on hand, forecast, the last-time-buy plan and the date the new build must ship.

How needCode helps

needCode runs chip migrations as Feature & Upgrade projects in four stages: a 2–4 week assessment, a phased port, validation and certification. Validation runs on hardware-in-the-loop benches with robotic positioning for TWR, TDoA and AoA. Certify handles FiRa, CCC, CSA and Bluetooth SIG work as one managed stage, which has shortened certification timelines by up to 40%. When the route is still open, a 2–4 week Product Assessment inventories parts and SDK versions with lifecycle status from your repositories, BOMs and release history, with no Qorvo involvement needed, and ends with a 90-day plan.

needCode is an official UWB business partner of Qorvo. Inside Qorvo’s UWB programme, our engineers developed firmware, drivers and protocol stacks for the QM33 and QM35, including a MAC layer built to the FiRa specification, and brought up nine hardware platforms. They work daily with Qorvo’s DW and QM series and Nordic nRF5x hosts. After release, a Sustain & Secure retainer covers SDK, RTOS and toolchain updates gated by hardware-in-the-loop tests.

Frequently asked questions

Is the Qorvo DW3120 end of life?

Yes. On 20 October 2026 Qorvo’s DW3120 page showed “Last Time Buy”, with “End of Life announced August 3, 2026” under PCN 26-0105 and a last time buy on 28 February 2027. The DW3220 has the same status and dates. Qorvo names no replacement on either page.

Is the whole DW3000 family end of life?

No. Only the two-antenna DW3120 and DW3220 carry the notice. The DW3110 and DW3210 showed “Production” on 20 October 2026, as did the DWM3000 and DWM3001C modules, which are built on the DW3110.

Is the QM33120W pin compatible with the DW3120?

At the footprint level, yes. A Qorvo staff reply calls the DW3000 CSP “pin2pin compatible” with the QM33, and the ball tables in both data sheets place every signal on the same ball. GPIO4, GPIO5 and GPIO6 have different functions, SPI mode is no longer set by pins, and the SPI clock limit falls to 32 MHz, so check the schematic.

What replaces the DW3220?

Qorvo names no replacement, and no QM33 part comes in QFN. The usual technical route is the QM33120W, which has two RF ports for PDoA but needs a new footprint and layout. Alternatives are last-time-buy stock, a QM33120W-based module, or the DW3210 where the second port is not needed.

Can one firmware image run on DW3000 and QM33 parts?

Yes, if it is built on the DW3_QM33 SDK with both the dw3000 and dw3720 drivers in the dwt_probe() list. The firmware must still handle differences the API does not hide, such as front-end GPIO roles, register-level code, the Japan pulse shape and per-chip calibration.

Why can a DW3xxx product not be sold in Japan?

According to Qorvo staff, DW3xxx parts do not support a pulse shape that complies with ARIB STD-T91. The QM33 parts do, through an alternative pulse shape on channel 9, and Qorvo staff recommend a band-pass filter to suppress out-of-band emissions.

Do we have to re-certify after moving to the QM33?

Plan for it. The radio changes, so plan new regulatory tests for each market. FiRa states that any change to a certified device requires re-certification; existing test results may be inherited, as FiRa decides case by case. Re-run Apple and Android interoperability tests with the new firmware.

Should we buy last-time-buy stock or redesign?

Buy stock if the product ends within the stock’s life or a redesign is already planned. Redesign if the product ships beyond that, needs Japan, or needs new features. Many teams do both: a buy sized to cover the gap until the redesigned product is certified.

Sources

  1. Qorvo product pages with PCN 26-0105 and last time buy dates: DW3120 and DW3220
  2. Qorvo product pages: DW3110 and DW3210
  3. Qorvo product pages: QM33110W and QM33120W
  4. Qorvo modules and kits: DWM3000, DWM3001C, DWM3001CDK and QM33120WDK1
  5. Qorvo QM35825 product page
  6. QM33120W Data Sheet Rev. D, October 2025 (distributor copy, LCSC)
  7. QM33110W Data Sheet Rev. B, October 2025 (distributor copy, Mouser)
  8. DW3000 Datasheet version 1.3, September 2022 (distributor copy, Mouser) and version 1.1, March 2021 (distributor copy)
  9. DW3xxx/QM33xxx Device Driver API Guide v4.9 (Qorvo Tech Forum attachment)
  10. Qorvo dwt_uwb_driver 08.02.02 from DW3_QM33_SDK_1.0.2, as published in a community Zephyr module: deca_device_api.h, dw3000_device.c, dw3720_device.c, dw3000_deca_regs.h and dw3720_deca_regs.h
  11. Qorvo Tech Forum: “New release of DW3000 and QM33 SDK: DW3_QM33 SDK v1.0.2” (September 2024)
  12. Qorvo Tech Forum: “Comparison between DWM3001C and InsightSIP ISP3080-UX” (Qorvo reply, July 2025)
  13. Qorvo Tech Forum: “DW3000 + external FEM (SW8112QF): TX fails after enabling PA path” (Qorvo reply, April 2026)
  14. Qorvo Tech Forum: “What is the difference between DW3120 and QM33120W?” (2022), “Datasheet full of mistakes, is there a newer Version available?” (2023) and “Missing functions in API header files” (2024)
  15. Qorvo Tech Forum: “Is it possible to get UWB certification of Japan with DW3210?” (2024) and “Dwm3001cdk japan support” (2023)
  16. Qorvo Tech Forum: “QM35825 Application development” (Qorvo reply, July 2025)
  17. Qorvo public GitLab group qorvo_sdk/public
  18. Qorvo PCN 25-0154: MDEK1001 end of life
  19. Murata: UWB modules with Qorvo chips (Type 2AB)
  20. FiRa Consortium: Certification FAQ
  21. Apple: Nearby Interaction for accessory manufacturers
  22. ETSI EN 302 065-1 V2.1.1 (2016-11)
  23. eCFR: 47 CFR 15.519, technical requirements for hand held UWB systems

About needCode

needCode is an independent embedded engineering company from Kraków, Poland, and an official UWB business partner of Qorvo. Its engineers have worked inside Qorvo’s wireless programmes for more than eight years, including on the public QM35 SDK. needCode is certified to ISO 9001:2015 and ISO/IEC 27001:2022 and is a member of the UWB Alliance. This page does not represent Qorvo. All trademarks belong to their respective owners.